1. Field of the Invention
The present invention relates to a reference voltage generator for generating bias reference voltages in a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional reference voltage generator.
The reference voltage generator has a P channel MOS transistor (hereinafter called “PMOS”) 1 that generates a constant voltage. The source of the PMOS1 is connected to a potential VDD and the gate and drain thereof are connected to a node N1. The node N1 is connected to a potential VEE through a current-limiting resistor 2. A first reference voltage VREF1 is outputted from the node N1. Further, the gate of a PMOS3 that constitutes a current mirror circuit with respect to the PMOS1 is connected to the node N1.
The source of the PMOS3 is connected to the potential VDD and the drain thereof is connected to a node N2, respectively. An N channel MOS transistor (hereinafter called “NMOS”) 4 diode-connected in a forward direction is connected between the node N2 and the potential VEE. A second reference voltage VREF2 is outputted from the node N2.
In this type of reference voltage generator, a current flows from the potential VDD to the potential VEE via the PMOS1 and the resistor 2. At this time, the voltage between the source and drain of the PMOS1 results in a threshold voltage Vtp of the PMOS1 regardless of the flowing current. Accordingly, the reference voltage VREF1 outputted to the node N1 results in a constant voltage reduced by the threshold voltage Vtp from the potential VDD.
On the other hand, a current proportional to the current of the PMOS1 flows into the PMOS3 that constitutes the current mirror circuit. The current of the PMOS3 flows toward the potential VEE via an NMOS4. At this time, the voltage developed between the drain and source of the NMOS4 results in a threshold voltage Vtn of the NMOS4 regardless of the flowing current. Accordingly, the reference voltage VREF2 outputted to the node N2 is brought to a constant voltage set high or increased by the threshold voltage Vtn from the potential VEE. Thus, the current-limiting resistor 2 restricts the reference current that flows through each of the PMOS1, PMOS3 and NMOS4, and the two types of reference voltages VREF1 and VREF2 can be generated with small current consumption.
However, when the difference between the potentials VDD and VEE is large, there is a need to increase the value of the resistor 2 in order to suppress the reference current, and hence a pattern area of an integrated circuit will increase.
Assuming that the reference current is set to 1 μA when VDD=+15V and VEE=−15V, for example, the value of the resistor 2 results in 30MΩ. Assuming that a W/L (=gate width/gate length) of the PMOS1 is 20 μm/7 μm, a W/L of the PMOS3 is 400 μm/7 μm and a W/L of the NMOS4 is 200 μm/7 μm, respectively, a region for the resistor 2 becomes 200 μm×200 μm=40,000 μm2, and regions for the transistors 1, 3 and 4 become 200 μm×50 μm=10,000 μm2, so that an approximate pattern area results in 50,000 μm2 in total.
On the other hand, when the region for the resistor 2 is reduced, a large resistance value cannot be obtained and hence current consumption will increase.